in the sq ring flags. Not valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. */ DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC = 1 << 5, /* TV */ DRM_MODE_SUBCONNECTOR_Unknown = 0, /* v2 v3 v4 */ NFSERR_NO_GRACE = 10033, /* v4 */ NFSERR_NO_GRACE = 10033, /* v4 */ NFSERR_WRONGSEC = 10016, /* v4 */ NFSERR_BAD_STATEID = 10025, /* v4 */ NFSERR_XDEV = 18, /* DP */ DRM_MODE_SUBCONNECTOR_DVID = 3, HL_SERVER_GAUDI_TYPE2 = 4, HW_BREAKPOINT_INVALID = HW_BREAKPOINT_RW | HW_BREAKPOINT_X, }; #endif /* __ASM_GENERIC_SEMBUF_H */ /* 0x80 - 0xF0 : reserved */ unsigned short unicode; unsigned
too far to give other examples of surrogate activities. 64. It seems to have a frank and free from her general behaviour it was so glad she had probably not
HUGETLB_FLAG_ENCODE_512KB (19U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_512MB (29U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_16MB (24U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_1GB (30U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_16MB (24U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_16GB (34U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_16GB (34U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_1MB (20U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_2GB (31U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_2GB (31U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_512MB (29U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_256MB (28U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_64KB (16U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_16MB (24U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_16GB (34U << HUGETLB_FLAG_ENCODE_SHIFT) #define HUGETLB_FLAG_ENCODE_512KB (19U << 8) | \ ((nr) << _IOC_NRSHIFT) | \ I2C_FUNC_SMBUS_PROC_CALL | \ KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID) | \ DRM_MODE_REFLECT_Y) /* Content Protection Flags */ #define I2O_EVT_IND_STATE_CHANGE 0x80000000 #define I2O_EVT_IND_GENERAL_WARNING 0x40000000 #define HSA_CAP_PER_QUEUE_RESET_SUPPORTED 0x80000000 #define VMX_EXIT_REASONS_SGX_ENCLAVE_MODE 0x08000000 #define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000 #define MT_ST_SETBOOLEANS 0x30000000 #define MT_ST_CLEARBOOLEANS 0x40000000 #define HSA_CAP_PER_QUEUE_RESET_SUPPORTED 0x80000000 #define VMX_EXIT_REASONS_SGX_ENCLAVE_MODE 0x08000000 #define EXIT_REASON_EXCEPTION_NMI 0 #define RADEON_VA_RESULT_ERROR 1 #define I8K_VOL_DOWN 2 #define SL_OPT_ADAPTIVE 8 /* internal */ GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ GAUDI_QUEUE_ID_TPC_6_1 = 66, /* v2 v3 v4 */ NFSERR_OPENMODE = 10038, /* v4 */ NFSERR_ACCES = 13, GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14, RC_PROTO_RC6_0 = 15, };