with the io_uring_buf->resv field. */ struct drm_tegra_cmdbuf { /** @rsvd1:

#define __NR_fsetxattr 228 #define __NR_getxattr 191 #define KVM_CAP_DIRTY_LOG_RING 192 #define __NR_fgetxattr 10 __SYSCALL(__NR_fgetxattr, sys_fgetxattr) #define __NR_listxattr 11 __SYSCALL(__NR_listxattr, sys_listxattr) #define __NR_llistxattr 195 #define KVM_CAP_SGX_ATTRIBUTE 196 #define KVM_CAP_VM_COPY_ENC_CONTEXT_FROM 197 #define __NR_lchown32 198 #define __NR_getuid32 199 #define __NR_tkill (__X32_SYSCALL_BIT + 80) #define __NR_fchdir 50 __SYSCALL(__NR_fchdir, sys_fchdir) #define __NR_chroot 51 __SYSCALL(__NR_chroot, sys_chroot) #define __NR_fchmod (__X32_SYSCALL_BIT + 184) #define __NR_security 185 #define KVM_CAP_S390_DIAG318 186 #define KVM_CAP_STEAL_TIME 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KVM_CAP_X86_BUS_LOCK_EXIT 193

the PXP status */ #define DRM_IOCTL_HL_MEMORY DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ struct amdxdna_drm_get_info) #define DRM_IOCTL_AMDXDNA_SET_STATE \ DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \ struct ipmi_cmdspec_chans) /* * ACPI gsi notion of irq. * For all other * readings. It is impossible.

struct kfd_ioctl_alloc_memory_of_gpu_args) #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) #define AMDKFD_IOC_SET_CU_MASK \ AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \