__NR_pkey_free 331 #define __NR_statx (__X32_SYSCALL_BIT + 135) #define __NR_ustat (__X32_SYSCALL_BIT + 30) #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) #define TP_STATUS_TS_SYS_HARDWARE (1 << 1), /* No hint */ #endif #ifndef __UAPI_DEF_IF_IFMAP #define __UAPI_DEF_IF_IFMAP 1 #define MRT6MSG_WRONGMIF 2 #define BIT_SEG14_D 3 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 #define VIDEO_CAP_PROG 8 /* The refill ring header size */ #define MAP_ASCII7SEG_ALPHANUM \ _MAP_0_32_ASCII_SEG7_NON_PRINTABLE \ _MAP_33_47_ASCII_SEG7_SYMBOL \ _MAP_48_57_ASCII_SEG7_NUMERIC \ _MAP_58_64_ASCII_SEG7_SYMBOL \ _SEG7(':',0,0,0,1,0,0,1), _SEG7(';',0,0,0,1,0,0,1), _SEG7('<',1,0,0,0,0,1,1),\ _SEG7('=',0,0,0,1,0,0,1), _SEG7('>',1,1,0,0,0,0,1), _SEG7('?',1,1,1,0,0,1,0),\ _SEG7('@',1,1,0,1,1,1,1), #define _MAP_65_90_ASCII_SEG7_ALPHA_UPPR \ _SEG7('A',1,1,1,0,1,1,1), _SEG7('B',1,1,1,1,1,1,1), _SEG7('C',1,0,0,1,1,1,0),\ _SEG7('D',1,1,1,1,1,1,0), _SEG7('E',1,0,0,1,1,1,1), _SEG7('F',1,0,0,0,1,1,1),\ _SEG7('G',1,1,1,1,0,1,1), _SEG7('H',0,1,1,0,1,1,1), _SEG7('I',0,1,1,0,0,0,0),\ _SEG7('J',0,1,1,1,0,0,0), _SEG7('K',0,1,1,0,1,1,1), _SEG7('L',0,0,0,1,1,1,0),\ _SEG7('M',1,1,1,0,1,1,0), _SEG7('n',0,0,1,0,1,0,1), _SEG7('o',0,0,1,1,1,0,1),\ _SEG7('P',1,1,0,0,1,1,1), _SEG7('q',1,1,1,0,0,1,1), _SEG7('r',0,0,0,0,1,0,1),\ _SEG7('S',1,0,1,1,0,1,1), _SEG7('T',0,0,0,1,1,1,1), _SEG7('U',0,1,1,1,1,1,0),\ _SEG7('V',0,1,1,1,1,1,0), _SEG7('W',0,1,1,1,1,1,1), _SEG7('X',0,1,1,0,1,1,1),\ _SEG7('Y',0,1,1,0,0,1,1), _SEG7('Z',1,1,0,1,1,0,1), #define _MAP_91_96_ASCII_SEG7_SYMBOL \ _SEG7('[',1,0,0,1,1,1,0), _SEG7('\\',0,0,1,0,0,1,1),_SEG7(']',1,1,1,1,0,0,0),\ _SEG7('^',1,1,0,0,0,1,0), _SEG7('_',0,0,0,1,0,0,0), _SEG7('`',0,1,0,0,0,0,0), #define _MAP_97_122_ASCII_SEG7_ALPHA_LOWER \ _MAP_91_96_ASCII_SEG7_SYMBOL \ _MAP_97_122_ASCII_SEG7_ALPHA_LOWER \ _MAP_123_126_ASCII_SEG7_SYMBOL #define SEG7_DEFAULT_MAP(_name) \ SEG7_CONVERSION_MAP(_name,MAP_ASCII7SEG_ALPHANUM) #endif /* _FWCTL_PDS_H_ */ /* #undef WITH_NEXT_FRAMEWORK */
base and extension */ #define ELOOP 40 /* tex4/6 */ #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', 'A', '8') #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '0', '8') #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', '1', '2') /* [63:0] A:R:G:B 16:16:16:16 little endian * index 1 = Cr plane, [15:0] Cb:Cr little endian */ #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) /* Deprecated. Instead set * for (j = 0; \ st.__unused[2] = 0; \ struct amdxdna_drm_config_hwctx) #define DRM_IOCTL_AMDXDNA_CREATE_BO \ DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) #define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) #define DRM_IOCTL_RADEON_GEM_PWRITE