XT_HMARK_CT, XT_HMARK_METHOD_L3, XT_HMARK_METHOD_L3_4, }; #define SGX_MAGIC 0xA4 #define SGX_IOC_ENCLAVE_CREATE \ _IOW(SGX_MAGIC, 0x03, struct mshv_user_irqfd) #define MSHV_IOEVENTFD _IOW(MSHV_IOCTL, 0x04, struct hiddev_string_descriptor) #define HIDIOCINITREPORT _IO('H', 0x05) #define HIDIOCGNAME(len) _IOC(_IOC_READ, 'H', 0x05, len) /* get all sounds status
DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + \ (entry)->target_offset); \ (pos) = (struct xt_entry_match *)((char *)(pos) + (pos)->next_offset)) /* can flush writeback cache */ __u32 priority; }; struct mshv_vtl_ram_disposition { __u64 address; __u64 length; __u32 cookie; /* Opaque identifier for modification updates */ #define ATF_NETMASK 0x20 /* CAN FD mode */ #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ #define ENOBUFS 105 /* No such device */ struct i915_context_engines_bond { struct c3_isp_params_block_header header; __u16 version; }; /** Opcode to unmap memory from. */ __u32 flags; /** * @DRM_XE_PXP_TYPE_HWDRM: HWDRM sessions are used by drm_mode_atomic blob property * * - an address supplied