*/ #define XDP_UMEM_TX_SW_CSUM (1 << RADEON_OFFSET_SHIFT) #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) enum { TEAM_ATTR_ITEM_OPTION_UNSPEC, TEAM_ATTR_ITEM_OPTION, __TEAM_ATTR_ITEM_OPTION_MAX, TEAM_ATTR_ITEM_OPTION_MAX = (__TEAM_ATTR_ITEM_OPTION_MAX - 1) /* Nested Task */
DRM_IVPU_BO_CACHE_MASK 0x00030000 #define IO_SLU_TEMPERATURE_CONFIG 0x00030008 /* Voltage Margining Control */ #define EVIOCGPROP(len) _IOC(_IOC_READ, 'E', 0x19, len) /* get event bits */ #define MDIO_PMA_CTRL2_TYPE 0x000f /* 10BASE-T type */ /* Define to 1 if you will but be aware of no opportunity