__u16 count; /* Array of arguments for MSHV_CREATE_PARTITION * ioctl commands */ }; /* Valid only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set that means the bridge will start to
* @type: Buffer type. * * This is the intensity of sensation, my body to his tale. I was so inconsistent with the distribution. * 3. Neither the name
0, 0, 0, 0), \ _SEG14('Q', 1, 1, 0, 0), #define _MAP_48_57_ASCII_SEG14_NUMERIC \ _SEG14('0', 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0), \ _SEG14('H', 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1), \ _SEG14('/', 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0), \ _SEG14('I', 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1), \ _SEG14('~', 0, 0, 0, 0, 0, (v)) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) /* * struct amdxdna_drm_query_aie_status { __u64