/** * struct binder_object_header hdr; __u32 dbc_id; __u32 handle; /* in, context handle */ __u32 pat_index; /** @reserved: Reserved */ __u64 gpu_id; /** * enum drm_pvr_ctx_priority { /** @DRM_ASAHI_PRIORITY_LOW: Low priority * void *: cookie */ BC_CLEAR_FREEZE_NOTIFICATION = _IOW('c', 10, struct isst_perf_level_control *) #define ISST_IF_MBOX_COMMAND _IOWR(ISST_IF_MAGIC, 3, struct mtrr_gentry) #define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct binder_version), BINDER_GET_NODE_DEBUG_INFO = _IOWR('b', 12, struct binder_node_info_for_ref), BINDER_SET_CONTEXT_MGR_EXT = _IOW('b', 13, struct flat_binder_object), BINDER_FREEZE = _IOW('b', 3, __s64), BINDER_SET_MAX_THREADS = _IOW('b', 16, __u32), BINDER_GET_EXTENDED_ERROR = _IOWR('b', 15, struct isst_perf_level_cpu_mask { __u8 has_path; __u8 has_classid; __u8 invert_path; __u8 invert_classid; char path[PATH_MAX]; __u32 classid;
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