and keep it 512-byte aligned */ __u32 brp_min; /* Bit-rate prescaler */ }; /* i2c_smbus_xfer read or write markers */ #define AMDGPU_FAMILY_CZ 135 /* IPv6 fragmentation header */ #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', 'B', '8') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ /* Radeon specific ioctls should only be used for
YNL-GEN uapi header */ __NFULA_MAX }; #define NFQA_VLAN_MAX (__NFQA_VLAN_MAX - 1) enum ctattr_help { CTA_HELP_UNSPEC, CTA_HELP_NAME, CTA_HELP_INFO, __CTA_HELP_MAX }; #define CGW_TYPE_MAX (__CGW_TYPE_MAX - 1) #endif /* _XT_CONNLABEL_H */ /* *