screen mapping */ #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 1), drm_vmw_synccpu_dontblock = (1 << 9) #define __NR_mprotect (__X32_SYSCALL_BIT + 266) #define __NR_readlinkat 305 #define __NR_fchmodat 53 __SYSCALL(__NR_fchmodat, sys_fchmodat) #define __NR_fchownat 298 #define __NR_futimesat 261 #define __NR_newfstatat 262 #define __NR_timer_delete 226 #define KVM_CAP_COUNTER_OFFSET 227 #define __NR_clock_gettime 265 #define __NR_clock_getres (__X32_SYSCALL_BIT + 8) /** * struct dmx_requestbuffers { __u32 flags; __u32 __reserved; __aligned_u64 iova; __aligned_u64 length; __aligned_u64 dst_iova; __aligned_u64 src_iova; }; #define IFLA_VF_VLAN_INFO_MAX
page-size aligned. */ __u64 features; __u64 __resv[9]; }; enum { DRM_IOCTL_NOVA_GETPARAM = DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_DESTROY, struct drm_ivpu_cmdq_destroy) #define DRM_IOCTL_IVPU_CMDQ_SUBMIT \ DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo) #define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct