'mbrtowc' function. */ #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf #define MTK_FMT_MOD_TILE_NONE 0x0 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 #define RADEON_GEM_DOMAIN_VRAM 0x4 struct drm_radeon_gem_info { __u64 handles; /* absolute */ }; struct drm_amdgpu_gem_list_handles_entry { /* Handle of CB */ #define IGNCR 0x080 /* * Gaudi queue Numbering * * Number of queries */ __u32 lessee_id; }; /** * struct amdxdna_drm_query_aie_tile_metadata { __u16 x, y; /* Blit coordinates */ unsigned char task_ioreg_t; typedef unsigned char ar_sip[4]; /* sender IP address */ IPVS_DEST_ATTR_STATS64, /* nested */ NET_DM_ATTR_HW_ENTRY, /* nested
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