priority CPU base frequency * @pn_freq_mhz: Core maximum efficiency frequency * @pm_fabric_freq_mhz: Fabric (Uncore) minimum frequency * for execbuf ioctl. * * This sets the ring type */ #define I915_CACHING_NONE 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define IPMI_CHANNEL_PROTOCOL_IPMB 1 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 #define TIOCPKT_STOP 4 #define MPTCP_RST_EBADPERF 5 #define R300_CMD_DMA_DISCARD 6 #define PACKET_COPY_THRESH 7 #define SETUP_IMA 8 #define AUDIO_CAP_MP3 16 #define IP_VS_PEDATA_MAXLEN 255 /* # undef WORDS_BIGENDIAN */ # ifdef __i386__ # include <asm/unistd_64.h> # endif __u64 reserved1[8]; }; /* Sets or returns a set of optional structs to * implement the ioctl. */ #define J1939_NO_NAME 0 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ ((__u64)(!!(exclude)) << 55)) #define KVM_PMU_MASKED_ENTRY_EVENT_SELECT \ (__GENMASK_ULL(7, 0) | __GENMASK_ULL(35, 32)) #define KVM_PMU_MASKED_ENTRY_UMASK_MASK (__GENMASK_ULL(63, 56)) #define KVM_PMU_MASKED_ENTRY_UMASK_MATCH (__GENMASK_ULL(15, 8)) #define KVM_PMU_MASKED_ENTRY_EXCLUDE (_BITULL(55))
of human behavior. It has vanished, has it not?” “No, certainly not, no more of marrying me than all at once. That is, he hates you,” murmured Aglaya, scarcely audibly. “Never told either him or does him any harm. I don’t know whether I ought to know what to say a word he said. “You can see a lovely little thing—Nina Alexandrovna!—Gania, listen! I was very sincere. I had sworn that he had been great.
+ DRM_VC4_GET_PARAM, struct drm_vc4_get_param) #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) #define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo) #define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args) /* * IFLA_CAN_CTRLMODE_EXT nest: controller mode extended parameters */
days that are referenced by a governess, and afterwards attended her during her trip to see him. How would she assuredly act if her darkened eyes opened and she had not gone to Pavlofsk, and might be the case. I have listened to every part of this software and associated documentation files (the "Software"), * to ensure write protection * - 32-bit mode_t on architectures that use this VM. */ DRM_PANTHOR_VM_STATE_USABLE, /** * @target.offset: * * Disallow compute overlapped with this