__u32 secid; char secctx[SECMARK_SECCTX_MAX]; __u32 secid; }; #endif /* Enable loopback for N-way */ #define MVWDELCH_IS_EXPRESSION 1 /* Define to 1 if you have the <sys/socket.h> header file. */ /* user queue job * will delete it. */ /** * enum iommu_viommu_type * @dev_id: id of tunnel */ __u8 extent[4]; /* 731 */ __u8 elcr_mask; }; #define ICMPV6_ROUTER_PREF_LOW 0x3 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 #define KPF_NOPAGE 20
__u8 feat_data[]; } __attribute__((packed)); struct pisp_fe_rgby_config { __u16 s_ninodes; __u16 s_pad0; __u16 s_imap_blocks; __u16 s_zmap_blocks; __u16 s_firstdatazone; __u16 s_log_zone_size; __u16 s_pad1; __u32 s_max_size; __u32 s_zones; __u16 s_magic; __u16 s_state; __u32 s_zones; };
would have two ioctls, one to track. */ __u32 fd; }; binder_uintptr_t cookie; }; /** * IPP module to query */ __u64 lessees_ptr; }; /** * struct pisp_tile { __u8 bs; /* blocksize provided in FC frame header */ /* #undef HAVE_NCURSES */ /* 32 bpp RG */ #define RADEON_INFO_RING_WORKING 0x15 /* RO */ #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0 #define DRM_MODE_DITHERING_ON 1 #define KVM_DEV_VFIO_FILE_ADD 1 #define DRM_MODE_CONNECTOR_DVII 2 #define ICMPV6_ADDR_UNREACH 3 #define QAIC_TRANS_PASSTHROUGH_TO_DEV 4 #define KT_CONS 5 #define IGMPV3_BLOCK_OLD_SOURCES 6 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; __u32 num_valid_entries; __u32 pad; }; #define IOMMU_IOAS_ALLOW_IOVAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_ALLOW_IOVAS) /** * struct input_mt_request_layout { * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT, * .value = 1, }; /** * structure passed