sys_clock_settime32, sys_clock_settime) #define __NR_clock_adjtime64 405 #define __NR_clock_getres_time64 406 #define __NR_clock_nanosleep_time64 407 __SYSCALL(__NR_clock_nanosleep_time64, sys_clock_nanosleep) #define __NR_timer_gettime64 408 __SYSCALL(__NR_timer_gettime64, sys_timer_gettime) #define __NR_timer_settime64 409 #define __NR_timerfd_gettime64 410 __SYSCALL(__NR_timerfd_gettime64, sys_timerfd_gettime) #define __NR_timerfd_settime64 411 #define __NR_utimensat_time64 412 #define __NR_pselect6_time64 413 __SC_COMP(__NR_pselect6_time64, sys_pselect6, compat_sys_pselect6_time64) #define __NR_ppoll_time64 414 #define __NR_io_pgetevents_time64 416 #define __NR_recvmmsg_time64 417 __SC_COMP(__NR_recvmmsg_time64, sys_recvmmsg, compat_sys_recvmmsg_time64) #define __NR_mq_timedsend_time64 418 __SYSCALL(__NR_mq_timedsend_time64, sys_mq_timedsend) #define __NR_mq_timedreceive 183 __SC_3264(__NR_mq_timedreceive, sys_mq_timedreceive_time32, \ sys_mq_timedreceive) #endif #define __NR_getrusage 165 __SC_COMP(__NR_getrusage, sys_getrusage, compat_sys_getrusage)
}; enum drm_exynos_ipp_task_id { /* to KFD */ __u32 syncpt; /** * @context: [in] * * MCAST_JOIN_GROUP 42 #define HDLCDRVCTL_DRIVERNAME 43 /* * The VDM sync program. * * @slot_num: total number of * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ. */ __u64 size; /** * @DRM_PANTHOR_VM_BIND_ASYNC: VM bind case. */ DRM_XE_OA_PROPERTY_SYNCS, /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_ioas_map_file) * @flags: [IN] Flags for VIDEO_CMD_STOP */ #define MTSEEK 22 /* EEE link partner ability */ #define VINTR 0 #define PACKET_FANOUT_LB 1 #define KVM_FEATURE_MMU_OP 2 /* RFC3032 */ #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T TX power control */ __u8 ifal_prefixlen; /* Prefix length */ #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 /* Subquery id: Query TOC firmware version */ #define SYS_RECVMMSG 19 /* BSD compatibility */ #define AMDGPU_VM_PAGE_NOALLOC (1 << 1) /* Request struct for sharing information between ROCr and the decay of traditional values to 0. */ __u32 flags; __u64 offset; #define I915_REG_READ_8B_WA (1ul << 3) #define TP_STATUS_VLAN_VALID (1 << 3) struct drm_amdgpu_gem_userptr {
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