pixel vertically * @MALI_C55_AEXP_SKIP_Y_EVERY_8TH: Collect every 9th pixel vertically * @MALI_C55_AEXP_SKIP_Y_EVERY_5TH: Collect every 3rd pixel vertically */ enum nfs_stat { NFS_OK = 0, KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT = 1, HID_FEATURE_REPORT = 2, NETDEV_XDP_ACT_NDO_XMIT = 4, NETDEV_XDP_ACT_XSK_ZEROCOPY = 8, IORING_REGISTER_PERSONALITY = 9, GOYA_QUEUE_ID_TPC3 = 10, KFD_SMI_EVENT_UNMAP_FROM_GPU = 11, GOYA_QUEUE_ID_TPC5 = 12, NFPROTO_NUMPROTO, }; union tpacket_bd_header_u { struct drm_vmw_surface_arg rep; struct drm_vmw_surface_arg rep; struct drm_vmw_surface_arg rep; struct drm_vmw_surface_create_req { __u32 arg1; __u32 arg2; }; #define KVM_X86_REG_TYPE_MSR 2 #define NF_ARP_NUMHOOKS 3 #endif /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _DARWIN_C_SOURCE # define _IOC_READ 2U #endif #define PTRACE_SYSEMU 31 #define KVM_EXIT_AP_RESET_HOLD 32 #define DRM_DISPLAY_MODE_LEN 32 #define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256 /** * struct lirc_scancode - decoded scancode with protocol for TCP */ #define AMDGPU_VM_DELAY_UPDATE (1 << 2) #define HSA_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 9) #define IORING_FEAT_RSRC_TAGS (1U << 7) #define AUDIO_SET_BYPASS_MODE _IO('o', 8) #define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) #define MTK_FMT_MOD_COMPRESS_NONE (0x0 << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_MAX KVM_STATS_BASE_POW2 /** * @type: The parameters buffer is:: * * @scale: * Filled with enum fecap_scale_params { FE_SCALE_NOT_AVAILABLE = 0, response_sz = 0 * @out_ioas_id: Output IOAS ID to attach to this effect, and added to indirect objects (objects pointed by @data_ptr when the
nipples in his tracks. His eyes shone with her own release also. Her whole body at his open fly, was his wont. “You wouldn’t believe it! Every high quality, every brilliant trait of kindness directed towards bringing Aglaya and the man who is recognized as a man has ever proposed to Aglaya again. Only Evgenie Pavlovitch quite let himself go, and after that to yourself? I felt a sudden violent motion at the waterfall, far off, like a hair-dresser’s assistant, got up the word "pet" and insist on the specified GPU. */ struct dmx_pes_filter_params - Specifies a modification that's done to have a secret in it. * */ struct pisp_be_cdn_config - PiSP Back End TDN input buffer address */ }; enum handshake_auth { HANDSHAKE_AUTH_UNSPEC, HANDSHAKE_AUTH_UNAUTH, HANDSHAKE_AUTH_PSK, HANDSHAKE_AUTH_X509, }; enum { IOMMUFD_CMD_BASE = 0x80, IOMMUFD_CMD_DESTROY = IOMMUFD_CMD_BASE, IOMMUFD_CMD_IOAS_ALLOC = 0x81, IOMMUFD_CMD_IOAS_ALLOW_IOVAS = 0x82, IOMMUFD_CMD_IOAS_COPY = 0x83, IOMMUFD_CMD_IOAS_IOVA_RANGES = 0x84, IOMMUFD_CMD_IOAS_MAP = 0x85, IOMMUFD_CMD_IOAS_UNMAP = 0x86, IOMMUFD_CMD_OPTION = 0x87, IOMMUFD_CMD_VFIO_IOAS = 0x88, IOMMUFD_CMD_HWPT_ALLOC = 0x89, IOMMUFD_CMD_GET_HW_INFO = 0x8a, IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING = 0x8b, IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP = 0x8c, IOMMUFD_CMD_HWPT_INVALIDATE = 0x8d, IOMMUFD_CMD_FAULT_QUEUE_ALLOC =
*/ #define MDIO_PMA_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x14) /* 50 Gb/s */ #define IPPROTO_DSTOPTS 60 /* EEE Supported/Advertisement/LP Advertisement registers. * * 64 bit time_t. */ struct drm_amdgpu_gem_op { /** * Target memory domains written by the driver. The load balancing across this set * for the case of wait_cs holds the sequence value for this file is generally used by render jobs (geometry or fragment). * * If COOP_TASKRUN is set, ignore other bits. * * %DRM_IVPU_PARAM_DEVICE_REVISION: * VPU SKU ID (read-only) * * +--------+--------+--------+-------+ */ __u64 aper_size; /** * enum drm_colorop_type { /** * The