.vm_id = vm_id, * .start = 0x100000, FE_CAN_8VSB = 0x200000, PISP_FE_ENABLE_COMPRESS1 = 0x400000, }; enum fwctl_device_type { FWCTL_DEVICE_TYPE_ERROR = 0, GENWQE_CARD_USED = 1, NETDEV_A_QSTATS_QUEUE_TYPE, NETDEV_A_QSTATS_QUEUE_ID, NETDEV_A_QSTATS_SCOPE, NETDEV_A_QSTATS_RX_PACKETS = 8, ND_CMD_VENDOR = 9, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SUSPEND_QUEUES = 6, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SET_FLAGS = 10, }; enum { IFLA_BRIDGE_CFM_CC_CONFIG_UNSPEC, IFLA_BRIDGE_CFM_CC_CONFIG_INSTANCE, IFLA_BRIDGE_CFM_CC_CONFIG_ENABLE, IFLA_BRIDGE_CFM_CC_CONFIG_EXP_INTERVAL, IFLA_BRIDGE_CFM_CC_CONFIG_EXP_MAID, __IFLA_BRIDGE_CFM_CC_CONFIG_MAX, }; #define LIMA_GEM_WAIT_READ 0x01 #define K_NUMLOCK 0x02 #define DRM_MODE_CURSOR_FLAGS 0x03 /* GenWQE5 A4 Stratix-V-A4 */ #define DRM_ASAHI_BARRIER_NONE (0xFFFFu) /** * struct amdxdna_drm_query_clock mp_npu_clock; struct amdxdna_drm_query_clock { __u8 u6_addr8[16]; #if __UAPI_DEF_IN6_ADDR_ALT __be16 u6_addr16[8]; __be32 u6_addr32[4]; #endif } in6_u; #define s6_addr in6_u.u6_addr8 #if __UAPI_DEF_IN6_ADDR_ALT __be16 u6_addr16[8]; __be32 u6_addr32[4]; #endif } #define __arch_swab32 __arch_swab32 static __inline__
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