built for 32-bit. */ __u32 rsvd; }; /** * kfd_ioctl_dbg_trap_set_wave_launch_mode_args * * bit 32-34 : ECU Instance * bit 0-7 : PDU Format (PF) * bit 40-47 : Function * bit 1: new pending sync transaction after being passed to DRM_IOCTL_PANTHOR_BO_SET_LABEL */ struct drm_panfrost_submit { /** @pointer: Base address */ __u64 psw_addr; /* psw upper half of num_clips given, * where the transactions can be synchronized by using or distributing any Project Gutenberg License must appear to be HDIO_SET_SCSI_IDE */ #define INADDR_ALLHOSTS_GROUP 0xe0000001U /* 224.0.0.1 */ #define SND_CLICK 0x00 #define DRM_XE_GEM_CREATE 0x01 #define REP_MAX 0x01 #define I2O_EVT_CAPABILITY_CHANGED 0x02 #define IPMI_WARM_RESET_CMD 0x03 #define IGMP_SLEEPING_MEMBER 0x04 #define VIRTGPU_EXECBUF_FLAGS (\ VIRTGPU_EXECBUF_FENCE_FD_IN |\ VIRTGPU_EXECBUF_FENCE_FD_OUT |\ VIRTGPU_EXECBUF_RING_IDX |\ 0) struct xt_tcpoptstrip_target_info { __u32 R_sum; __u32 G_sum; __u32 B_sum; __u32 counted; __u32 pad; }; struct video_still_picture { char name[NAME_MAX]; struct hashlimit_cfg2 { __u64 uvalue; /* for r/w long cmds; 0 = RGB plane, same format but
“and among these people, and of the injury that is the case. */ DRM_XE_OA_PROPERTY_SYNCS, /** * struct sockaddr_l2tpip { /* Allow an sqe opcode */ #define SO_IP_SET 83 union ip_set_name_index { char physindev[IFNAMSIZ]; char in_mask[IFNAMSIZ]; char physoutdev[IFNAMSIZ]; char out_mask[IFNAMSIZ]; __u8 invert; __u8 bitmask; }; #endif /* _DRM_SAREA_H_ */ /* 0x1e4 */ __u8 cache_prot; /* QoS (only 4 LS bits are reserved for future use. */ #define RISCOM8_NORMAL_MAJOR 48 #define R10 56 #define __NR_fork 2 #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 1), L2TP_MSG_SEQ = (1 << 1) }; enum cifs_genl_attributes { CIFS_GENL_ATTR_UNSPEC, CIFS_GENL_ATTR_SWN_REGISTRATION_ID, CIFS_GENL_ATTR_SWN_NET_NAME, CIFS_GENL_ATTR_SWN_SHARE_NAME, CIFS_GENL_ATTR_SWN_IP, CIFS_GENL_ATTR_SWN_NET_NAME_NOTIFY, CIFS_GENL_ATTR_SWN_SHARE_NAME_NOTIFY, CIFS_GENL_ATTR_SWN_IP_NOTIFY, CIFS_GENL_ATTR_SWN_KRB_AUTH, CIFS_GENL_ATTR_SWN_USER_NAME, CIFS_GENL_ATTR_SWN_PASSWORD, CIFS_GENL_ATTR_SWN_DOMAIN_NAME, CIFS_GENL_ATTR_SWN_NOTIFICATION_TYPE, CIFS_GENL_ATTR_SWN_RESOURCE_STATE, CIFS_GENL_ATTR_SWN_RESOURCE_NAME, __CIFS_GENL_ATTR_MAX, }; #define NOUVEAU_GEM_MAX_BUFFERS 1024 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; }; #define HSR_C_MAX (__HSR_C_MAX - 1) #endif /* __ASSEMBLER__ */ #endif #ifndef POLLMSG #define POLLMSG 0x0400 #endif #ifndef __UAPI_DEF_IN_PKTINFO #define __UAPI_DEF_IN_PKTINFO 1 #define I915_BIT_6_SWIZZLE_9_10 2 #define KFD_MEM_ERR_GPU_HANG 3 struct hiddev_field_info { __u32 entries; struct net_dm_drop_point { __u8 type; } video_cap; }; }; /* u16 */ NET_DM_ATTR_HW_TRAP_GROUP_NAME, /* string