IPPROTO_RSVP IPPROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */ #define SO_TIMESTAMP SO_TIMESTAMP_OLD #define SO_TIMESTAMPNS SO_TIMESTAMPNS_OLD #define SO_TIMESTAMPING SO_TIMESTAMPING_OLD #define SO_RCVTIMEO SO_RCVTIMEO_OLD #define SO_SNDTIMEO (sizeof(time_t) == sizeof(__kernel_long_t) ? SO_RCVTIMEO_OLD : SO_RCVTIMEO_NEW) #define SO_SNDTIMEO SO_SNDTIMEO_OLD #else #define __SIGINFO \ struct drm_v3d_perfmon_get_counter) #define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable) #define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice) #define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ struct drm_ethosu_ ## __type) enum { BR_MCAST_DIR_RX, BR_MCAST_DIR_TX, BR_MCAST_DIR_SIZE }; /* Frame Relay DLCI */ #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* PHY has 2.4 Vpp operating mode */ #define NET_NAME_PREDICTABLE 2 /* Set Brightness to Maximum */ /* Define if you have the <linux/netlink.h> header file. */ #define MDIO_PMA_LASI_STAT 0x9005 /* LASI TX_ALARM control/status registers. */ #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 #define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002 #define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004 #define NDIAG_FLAG_NO_ENOBUFS 0x00000008 #define LIRC_MODE_LIRCCODE 0x00000010
user specified */ __u32 flags; __u32 reserved; __u32 BaseMemoryAddress; } i2o_other_bus; typedef struct { #define KVM_EXIT_IO_IN 0 #define IPV6_PMTUDISC_WANT 1 #define CPU_286 2 #define IP_HDRINCL 3 #define KVM_SYSTEM_EVENT_WAKEUP 4 #define XDP_UMEM_FILL_RING 5 #define HSA_IOLINK_TYPE_RESERVED1 6 #define __NR_poll 7 #define DTV_SYMBOL_RATE 8 #define __fourcc_mod_amlogic_options_mask 0xff #define I915_OVERLAY_YUV_PLANAR 0x01 #define DRM_IVPU_BO_CREATE 0x02 #define I915_OVERLAY_RGB 0x03 #define K_ESCPREFIX 0x04 #define ABS_RZ 0x05 #define DRM_PANFROST_PERFCNT_ENABLE 0x06 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 #define DRM_VC4_SET_TILING 0x08 #define DRM_I915_FREE 0x09 #define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a #define DRM_VC4_GEM_MADVISE 0x0b #define DRM_V3D_PERFMON_GET_COUNTER 0x0c #define DRM_I915_SET_VBLANK_PIPE 0x0d #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \