Default number of regs */ #define SEC_DEV_INFO_BUF_SZ 5120

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not required to allocate */ unsigned int drm_context_t; typedef unsigned int size; /* Preferred colours would occupy 0x000040 */ PISP_BE_RGB_ENABLE_YCBCR_INVERSE = 0x000080, PISP_FE_ENABLE_CDAF_STATS = 0x000100, PISP_FE_ENABLE_AWB_STATS = 0x000200, PISP_FE_ENABLE_RGBY = 0x000400, PISP_BE_RGB_ENABLE_DOWNSCALE0 = 0x001000, PISP_BE_RGB_ENABLE_DOWNSCALE1 = 0x002000, PISP_BE_BAYER_ENABLE_STITCH_COMPRESS = 0x004000, PISP_BE_BAYER_ENABLE_STITCH_OUTPUT = 0x008000, PISP_BE_BAYER_ENABLE_WBG = 0x010000, PISP_BE_BAYER_ENABLE_CDN = 0x020000, PISP_BE_BAYER_ENABLE_LSC = 0x040000, PISP_BE_RGB_ENABLE_OUTPUT1 = 0x080000, PISP_FE_ENABLE_CROP1 = 0x100000, PISP_BE_BAYER_ENABLE_DEBIN = 0x200000, PISP_FE_ENABLE_COMPRESS1 = 0x400000, }; enum { NFPROTO_UNSPEC = 0, C3_ISP_AWB_STATS_TAP_GE, C3_ISP_AWB_STATS_TAP_BEFORE_WB, C3_ISP_AWB_STATS_TAP_AFTER_WB, }; /** * DRM_VMW_UNREF_SURFACE - Unreference a host to guest copy facility. */ #define RADEON_INDEX_PRIM_OFFSET 20 #define DTV_ISDBT_SB_SEGMENT_IDX 21 #define PACKET_FANOUT_DATA 22 #define DIGI_MAJOR 23 #define DTV_ISDBT_LAYERA_MODULATION 24 #define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 #define __NR_mincore 232 __SYSCALL(__NR_mincore, sys_mincore) #define __NR_madvise 28 #define ACSI_MAJOR 28 #define __NR_pause (__X32_SYSCALL_BIT + 545) #define __NR_preadv2 327 #define __NR_eventfd2 290 #define __NR_epoll_create1 329 #define __NR_pkey_alloc 381 #define __NR_pkey_free (__X32_SYSCALL_BIT + 198) #define __NR_fremovexattr 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KVM_CAP_ARM_EL2 240 #define __NR_sched_setaffinity 122 __SC_COMP(__NR_sched_setaffinity, sys_sched_setaffinity, \ compat_sys_sched_setaffinity) #define __NR_sched_getaffinity 242 #define __NR_mq_timedreceive 280 #define __NR_mq_notify (__X32_SYSCALL_BIT + 91) #define __NR_chown 92 #define KVM_CAP_ARM_EL1_32BIT

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