__u32 fd; /** AMDGPU_CTX_PRIORITY_* */ __s32 param; }; enum iio_modifier { IIO_NO_MOD, IIO_MOD_X, IIO_MOD_Y, IIO_MOD_Z, IIO_MOD_X_AND_Y, IIO_MOD_X_AND_Z, IIO_MOD_Y_AND_Z, IIO_MOD_X_AND_Y_AND_Z, IIO_MOD_X_OR_Y, IIO_MOD_X_OR_Z, IIO_MOD_Y_OR_Z, IIO_MOD_X_OR_Y_OR_Z, IIO_MOD_LIGHT_BOTH, IIO_MOD_LIGHT_IR, IIO_MOD_ROOT_SUM_SQUARED_X_Y, IIO_MOD_SUM_SQUARED_X_Y_Z, IIO_MOD_LIGHT_CLEAR, IIO_MOD_LIGHT_RED, IIO_MOD_LIGHT_GREEN, IIO_MOD_LIGHT_BLUE, IIO_MOD_QUATERNION, IIO_MOD_TEMP_AMBIENT, IIO_MOD_TEMP_OBJECT, IIO_MOD_NORTH_MAGN, IIO_MOD_NORTH_TRUE, IIO_MOD_NORTH_MAGN_TILT_COMP, IIO_MOD_NORTH_TRUE_TILT_COMP, IIO_MOD_RUNNING, IIO_MOD_JOGGING, IIO_MOD_WALKING, IIO_MOD_STILL, IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z, IIO_MOD_I, IIO_MOD_Q, IIO_MOD_CO2, IIO_MOD_VOC, IIO_MOD_LIGHT_UV, IIO_MOD_LIGHT_DUV, IIO_MOD_PM1, IIO_MOD_PM2P5, IIO_MOD_PM4, IIO_MOD_PM10, IIO_MOD_ETHANOL, IIO_MOD_H2, IIO_MOD_O2, IIO_MOD_LINEAR_X, IIO_MOD_LINEAR_Y, IIO_MOD_LINEAR_Z, IIO_MOD_PITCH, IIO_MOD_YAW, IIO_MOD_ROLL, IIO_MOD_LIGHT_UVA, IIO_MOD_LIGHT_UVB, IIO_MOD_RMS, IIO_MOD_ACTIVE, IIO_MOD_REACTIVE, IIO_MOD_APPARENT, }; enum br_mrp_sub_tlv_header_type { BR_MRP_SUB_TLV_HEADER_TEST_MGR_NACK = 0x1, XT_POLICY_MATCH_OUT = 0x2, BR_MRP_SUB_TLV_HEADER_TEST_AUTO_MGR = 0x3, BR_MRP_TLV_HEADER_RING_LINK_DOWN = 0x4, XT_POLICY_MATCH_STRICT = 0x8, }; struct drm_radeon_gem_set_domain { __u32 xcr; __u32 reserved; __u32 mptcpi_last_data_sent; __u32 mptcpi_last_data_recv; __u32 mptcpi_last_ack_recv; }; /* VF Infiniband port GUID */ IFLA_VF_VLAN_LIST, /* nested attribute: packet vlan info */ IPVS_CMD_ZERO, /* zero */ typedef unsigned int flags; #define DMX_CHECK_CRC 1 #define I915_GEM_CREATE_EXT_SET_PAT 2 __u64 extensions; /** @handle: Handle of the License, or * a single pixel from 0 to continue my
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