IO_APP_DEBUG_REG_07 0x02010030 #define IO_APP_DEBUG_REG_08 0x02010038 #define IO_APP_DEBUG_REG_09 0x02010040 #define IO_APP_DEBUG_REG_10 0x02010048 #define IO_APP_DEBUG_REG_11 0x02010050 #define IO_APP_DEBUG_REG_12 0x02010058 #define IO_APP_DEBUG_REG_13 0x02010060 #define IO_APP_DEBUG_REG_14 0x02010068 #define IO_APP_DEBUG_REG_15 0x02010070 #define IO_APP_DEBUG_REG_16 0x02010078 #define IO_APP_DEBUG_REG_17 0x02010080 #define IO_APP_DEBUG_REG_18 0x02010088 /* Read/write from/to registers */ PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2, }; struct drm_block { int region; int size; /**< In bytes -- will round to page boundary */ }; #define MPTCP_PM_ENDPOINT_MAX (__MPTCP_PM_ENDPOINT_MAX - 1) /* [MDBA_GET_ENTRY] = { * .next_extension = to_user_pointer(&p_protected), * }, * }; * struct drm_vmw_fence_signaled_arg * * Number of event as defined by XENPAK MSA. */ #define IPV6_RECVTCLASS 66 #define DTV_STAT_POST_TOTAL_BIT_COUNT 67 #define DTV_STAT_ERROR_BLOCK_COUNT 68 #define
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