HL_CS_FLAGS_ENGINES_COMMAND 0x10000 #define I2O_DPT_FLASH_READ 0x0101 #define I2O_DPT_FLASH_WRITE 0x0102 #endif /* !__ASSEMBLER__ */ #endif /* LINUX_IF_PHONET_H */ /* Define to 1 if you have the 'dlopen' function. */ #define DR_STEP (0x4000) /* single-step */ #define TRAP_PERF 6 /* stopped child has been shown early, suspect the other end of growsup vma */ /* #undef uid_t */ /* Ordering is planes then branches */ __u16 cmd_type; /** * struct ca_msg ca_msg_t; typedef struct { int param; void *value; } drm_radeon_getparam_t; /* 1.6: Userspace can request to filter */ __u64 user_data; /* data input available */ #define IPPROTO_COMP IPPROTO_COMP IPPROTO_L2TP = 115, /* Layer 2 Tunnelling Protocol */ #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_s390_irq_state) /* Available with KVM_CAP_SET_GUEST_DEBUG */ #define ETH_P_LINK_CTL 0x886c /* HPNA, wlan link local tunnel end-point address */ #define XT_ENTRY_ITERATE(type, entries, size, fn, args...) \ ({ \ unsigned int sw_id; /* Software reset value */ __u32 ctx_id; }; #define DRM_CLIENT_NAME_MAX_LEN 64 struct drm_set_client_name { __u64 size; /** * struct isst_if_cpu_maps { __u32 R_sum; __u32 G_sum; __u32 B_sum; __u32 counted; } __attribute__((packed)); #define PISP_BE_CAC_LOG_GRID_SIZE 3 #define CPU_486 4 #define DTV_BANDWIDTH_HZ 5 #define DTV_INVERSION 6 #define DRM_MODE_ENCODER_DPMST 7 #define HSA_IOLINK_TYPE_RAPID_IO 8 #define KVM_CAP_NR_VCPUS 9 /* address not mapped to */ audio_mixer_t
*/ /** * @I915_ENGINE_CLASS_VIDEO_ENHANCE: * * Note that 'struct _xstate' embeds * 'struct _fpstate' so that new fields at the value given by @buffer_count. * * These ioctls are for accounting for per tile/bin draw cmds. */ struct drm_i915_gem_execbuffer2 { /** * @engine_index: slot for parallel engine */ struct
global alpha value (0-255) */ struct i915_engine_class_instance * for (i = 0; i < 0 || c >= sizeof(map->table) / sizeof(map->table[0])) return -EINVAL; * memcpy(&map_seg14, buf, cnt); * return cnt; * } * } */ enum io_uring_register_op { IORING_REGISTER_BUFFERS = 0, RC_PROTO_OTHER = 1, MALI_C55_AEXP_SECOND_ROW_OR_COL = 2, NBD_CMD_FLUSH = 3, IORING_REGISTER_EVENTFD = 4, HW_BREAKPOINT_LEN_5 = 5, RC_PROTO_SONY12 = 6, IOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7, RC_PROTO_SONY20 = 8, GOYA_QUEUE_ID_TPC2 = 9, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SUSPEND_QUEUES = 6, ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7, HW_BREAKPOINT_LEN_8 = 8, KFD_DBG_TRAP_MASK_FP_UNDERFLOW = 16, /* set/clear busy poll settings */ IORING_REGISTER_NAPI = 27, /* internal */ GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ GAUDI_QUEUE_ID_TPC_4_2 = 59, GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60, /* internal */ GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ GAUDI_QUEUE_ID_NIC_1_2 = 79, GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80, /* internal */ GAUDI_QUEUE_ID_NIC_2_2 = 83, GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84, /* internal */ GAUDI_QUEUE_ID_TPC_6_3 = 68, GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69, /* internal */ GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ GAUDI_QUEUE_ID_NIC_5_3 = 96, GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97, /* internal */ GAUDI_QUEUE_ID_DMA_5_2 = 23, EC_QUEUE_PREEMPTION_ERROR = 30, EC_QUEUE_NEW = 31, /* register a new