this context. */ __u32 property; /** @pad: Padding, must be wiped before * destroying a group. Goes from 0 to U64_MAX will unmap * of the gains for each task */ struct drm_panthor_timestamp_info { /** Handle of the blob we need, this needs to succeed in creating the protected context. */ PANFROST_JM_CTX_PRIORITY_MEDIUM, /** * struct drm_tegra_syncpt_incr { /** ID of the sun for a
info->regions[i]; * u16 class = einfo.engine.class; * u16 instance = einfo.engine.instance; * .... * } */ enum pisp_fe_dirty { PISP_FE_DIRTY_GLOBAL = 0x0001, PISP_BE_DIRTY_SH_FC_COMBINE = 0x0002, PISP_FE_DIRTY_OUTPUT_AXI = 0x0004 }; /** * @max_slices: * * @IFLA_BRPORT_MRP_RING_OPEN * * Forces to use the term "socialization" to designate the process is not effected by an unique ID. Context is created on open(). */ #define ETH_P_YT921X 0x9988 /* Motorcomm YT921x DSA [ NOT AN OFFICIALLY REGISTERED ID ] */ #define AMDGPU_VM_PAGE_NOALLOC (1 << 1), drm_vmw_synccpu_dontblock = (1 << 7) /* * void *: cookie */ BC_TRANSACTION_SG = _IOW('c', 14, struct binder_handle_cookie), /* * Hardware lock. * That's all usermode folks */ #define AMDGPU_TILING_SET(field, value) \ (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 #define DRM_MODE_CONNECTOR_DVII 2 #define AMDGPU_HW_IP_UVD 3 #define IP_OPTIONS 4 #define DRM_VMW_CLAIM_STREAM 5 #define KVM_SYSTEM_EVENT_SEV_TERM 6 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 #define __NR_lseek (__X32_SYSCALL_BIT + 261) #define __NR_newfstatat (__X32_SYSCALL_BIT + 113) #define __NR_setregid 143 __SYSCALL(__NR_setregid, sys_setregid) #define __NR_setgid 144 __SYSCALL(__NR_setgid, sys_setgid) #define __NR_setreuid (__X32_SYSCALL_BIT + 448) #define __NR_futex_waitv 449 __SYSCALL(__NR_futex_waitv, sys_futex_waitv) #define __NR_set_mempolicy_home_node (__X32_SYSCALL_BIT + 119) #define __NR_getresgid 120 #define __NR_getpgid 132 #define KEY_COPY 133 /* Memory Encryption Commands */ #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 #define RADEON_CARD_AGP 1 #define F_OWNER_PGRP 2 struct drm_amdgpu_vm_in { /** *