#define IPV6_PRIORITY_UNCHARACTERIZED 0x0000 #define TASKFILE_IN 0x0001 #define POLLPRI 0x0002 #define IFF_NAPI 0x0010 #define IFF_NAPI_FRAGS 0x0020 /* Try for 1000BASE-X half-duplex */ #define SW_PEN_INSERTED 0x0f /* set = inserted */ #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 #define NFCT_HELPER_STATUS_ENABLED 1 enum handshake_handler_class { HANDSHAKE_HANDLER_CLASS_NONE, HANDSHAKE_HANDLER_CLASS_TLSHD, HANDSHAKE_HANDLER_CLASS_MAX, }; enum { NDA_UNSPEC, NDA_DST, NDA_LLADDR, NDA_CACHEINFO, NDA_PROBES, NDA_VLAN, NDA_PORT, NDA_VNI, NDA_IFINDEX, NDA_MASTER, NDA_LINK_NETNSID, NDA_SRC_VNI, NDA_PROTOCOL, /* Originator of entry */ #define ENOTTY 25 /* Encrypt a blob using a public key signature */ __u8
some integer. * On hw interrupt, it's IRQ number: */ #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 2.5GT EEE cap */ #define MDIO_PMA_EXTABLE_10BT 0x0100 /* Try for 1000BASE-X half-duplex */ #define IOPRIO_CLASS_SHIFT 13 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 #define KVM_CAP_COALESCED_MMIO 15 #define __NR_lchown 16 #define OPTICS_CDROM_MAJOR 17 #define BRCTL_GET_FDB_ENTRIES 18 #define HL_INFO_DRAM_REPLACED_ROWS 21 #define IDE1_MAJOR 22 #define DIGI_MAJOR 23 #define MITSUMI_CDROM_MAJOR 23 #define SIGXCPU 24 #define MATSUSHITA_CDROM_MAJOR 25 #define __NR_msync 144 #define RSP 152 #define SS 16 #define __NR_pread64 (__X32_SYSCALL_BIT + 190)