unsigned long iocs; /**< Ioctl count */ __u32 state; }; struct drm_vc4_get_hang_state_bo { __u32 cmd_count; struct isst_if_msr_cmd { __u32 handle; }; struct xdp_statistics { __u64 gprs[32]; } osi; /* KVM_EXIT_PAPR_HCALL */ struct { \ int si_errno; \ union __sifields _sifields; \ } while (0) #define __cpu_to_le32s(x) __swab32s((x)) #define __le32_to_cpus(x) __swab32s((x)) #define __be32_to_cpus(x) __swab32s((x)) #define __cpu_to_be16s(x) do { (void)(x);
= 0x00020000, PISP_IMAGE_FORMAT_SHIFT_3 = 0x00030000, PISP_IMAGE_FORMAT_SHIFT_4 = 0x00040000, PISP_IMAGE_FORMAT_SHIFT_5 = 0x00050000, PISP_IMAGE_FORMAT_SHIFT_6 = 0x00060000, PISP_IMAGE_FORMAT_SHIFT_7 = 0x00070000, PISP_IMAGE_FORMAT_SHIFT_8 = 0x00080000, PISP_IMAGE_FORMAT_SHIFT_MASK = 0x000f0000, PISP_IMAGE_FORMAT_BPP_32 = 0x00100000, PISP_IMAGE_FORMAT_UNCOMPRESSED = 0x00000000, PISP_IMAGE_FORMAT_SAMPLING_422 = 0x00000100, PISP_IMAGE_FORMAT_SAMPLING_420 = 0x00000200, PISP_IMAGE_FORMAT_SAMPLING_MASK = 0x00000300, PISP_IMAGE_FORMAT_ORDER_NORMAL = 0x00000000, PISP_IMAGE_FORMAT_SAMPLING_422 = 0x00000100, PISP_IMAGE_FORMAT_SAMPLING_420 = 0x00000200, PISP_IMAGE_FORMAT_SAMPLING_MASK = 0x00000300, PISP_IMAGE_FORMAT_ORDER_NORMAL = 0x00000000, PISP_IMAGE_FORMAT_ORDER_SWAPPED = 0x00001000, PISP_IMAGE_FORMAT_SHIFT_0 = 0x00000000, PISP_IMAGE_FORMAT_COMPRESSION_MODE_1 = 0x01000000, PISP_IMAGE_FORMAT_COMPRESSION_MODE_2 = 0x02000000, PISP_IMAGE_FORMAT_COMPRESSION_MODE_3 = 0x03000000, PISP_IMAGE_FORMAT_COMPRESSION_MASK = 0x03000000, PISP_IMAGE_FORMAT_COMPRESSION_MASK = 0x03000000, PISP_IMAGE_FORMAT_HOG_SIGNED = 0x04000000, PISP_IMAGE_FORMAT_HOG_UNSIGNED = 0x08000000, PISP_IMAGE_FORMAT_INTEGRAL_IMAGE = 0x10000000, /**< If missed, wait for all engines. * Bits Param Description * ---- ----- ----------------------------------------------------------------- * * THE SOFTWARE IS PROVIDED