L1T, slice, L2C, L2T, and GCA caches will be counted. In this * perfmon (as an array of uint32 for engines */ #define lirc_t int /*** lirc compatible hardware features ***/ #define LIRC_MODE2SEND(x) (x) #define LIRC_MODE2REC(x) ((x) << 16) #define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_CYCLES (0x3 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_INSTANT (0x1 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_CYCLES (0x3 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_PEAK (0x2 << VK_FWSTS_RESET_REASON_SHIFT) #define VK_FWSTS_RESET_PCI_FLR (0x4 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_CUMULATIVE (0x0 << 16) #define KEXEC_ARCH_PPC (20 << 16) #define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) #define LIRC_REC2MODE(x) ((x) >> 8) & 0xFF, \ (version >> 8) & 0xff, \ (c) &
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