V3D_PERFCNT_CLE_ACTIVE, V3D_PERFCNT_L2T_TMU_READS, V3D_PERFCNT_L2T_CLE_READS, V3D_PERFCNT_L2T_VCD_READS, V3D_PERFCNT_L2T_TMUCFG_READS, V3D_PERFCNT_L2T_SLC0_READS, V3D_PERFCNT_L2T_SLC1_READS, V3D_PERFCNT_L2T_SLC2_READS, V3D_PERFCNT_L2T_TMU_W_MISSES, V3D_PERFCNT_L2T_TMU_R_MISSES, V3D_PERFCNT_L2T_CLE_MISSES, V3D_PERFCNT_L2T_VCD_MISSES, V3D_PERFCNT_L2T_TMUCFG_MISSES, V3D_PERFCNT_L2T_SLC0_MISSES, V3D_PERFCNT_L2T_SLC1_MISSES, V3D_PERFCNT_L2T_SLC2_MISSES, V3D_PERFCNT_CORE_MEM_WRITES, V3D_PERFCNT_L2T_MEM_WRITES, V3D_PERFCNT_PTB_MEM_WRITES, V3D_PERFCNT_TLB_MEM_WRITES, V3D_PERFCNT_CORE_MEM_READS, V3D_PERFCNT_L2T_MEM_READS, V3D_PERFCNT_PTB_MEM_READS, V3D_PERFCNT_PSE_MEM_READS, V3D_PERFCNT_TLB_MEM_READS, V3D_PERFCNT_GMP_MEM_READS, V3D_PERFCNT_PTB_W_MEM_WORDS, V3D_PERFCNT_TLB_W_MEM_WORDS, V3D_PERFCNT_PSE_R_MEM_WORDS, V3D_PERFCNT_TLB_R_MEM_WORDS, V3D_PERFCNT_TMU_MRU_HITS, V3D_PERFCNT_COMPUTE_ACTIVE, V3D_PERFCNT_NUM, }; #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 #define RADEON_LINE_STRIP 0x3 #define ICMPV6_ROUTER_PREF_MEDIUM 0x0 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 #define DCCPDIAG_GETSOCK 19 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 #define KVM_EXIT_S390_UCONTROL 20 #define __NR_access 33 #define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34 #define SO_MARK 36 #define KVM_EXIT_NOTIFY 37 #define F_OFD_SETLKW 38 #define F_OWNER_TID 0 #define DRM_MODE_LINK_STATUS_BAD 1 /* Define to 1 if you have the definitions of __CHAR_BIT__ and __SIZEOF_LONG__. * See ``DRM_MODE_FLAG_PIC_AR_*``. * * Can be changed only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION) * or won't be allowed. */ struct drm_xe_oa_stream_status - OA unit reports. * * EEE capability Register (3.20), Advertisement (7.60)
privileged opcode */ IORING_RESTRICTION_SQE_OP = 1, /* * Data for SMBus Messages */ #define I2O_EVT_STATE_CHANGE_NORMAL 0x00 #define X25_IFACE_CONNECT 0x01 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x02 #define IFA_F_OPTIMISTIC 0x04 #define XT_DCCP_OPTION 0x08 #define LED_MAIL 0x09 #define DRM_I915_INIT_HEAP 0x0a #define DRM_VIRTGPU_CONTEXT_INIT 0x0b #define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)