}; /** * struct c3_isp_params_awb_config ----------+ | | | | * | | | | | 08-15 | LS1 | * 0.2 | * +-----------+------------+-------+--------------+ * | | 08-15 | LS1 | * | | 08-15 | LS1 | * +============+========================+========================+ * | 1023 | 31,31 | 16,23
* @cr_min: Minimum R/G ratio (Q4.8 format) * @gb_ofst: Gb blc offset(Q4.12 format) */ struct amdxdna_drm_query_firmware_version { __u32 id; __u64 addr; } __attribute__((packed)); /* * Allwinner tiled modifier * * For encap,auto modes. * See architecture code for this * channel. */ __u32 width; __u32 height; __s32 stride; __u32 layer_stride; }; struct drm_mode_get_blob { __u32