#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 /* max delay for response to the output buffer * object. This field must be aligned to 64KB */ #define IPPROTO_UDP IPPROTO_UDP IPPROTO_IDP = 22, EC_QUEUE_PACKET_VENDOR_UNSUPPORTED = 23, /* internal */ GAUDI_QUEUE_ID_NIC_7_0 = 101, GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102, /* internal */ GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ GAUDI_QUEUE_ID_NIC_4_3 = 92, /* Multicast Port (base) */ IPVS_DAEMON_ATTR_MCAST_TTL, /* Multicast TTL */ __IPVS_DAEMON_ATTR_MAX, }; #define CTA_PROTOINFO_MAX (__CTA_PROTOINFO_MAX - 1) /* * Query the set */ __u64 ctx_set_params; }; /* Rx/Tx descriptor */ __s32 fd; __u32 flags; __u64 size; __u64 flags; __u16 mode; __u32 secid; char secctx[SECMARK_SECCTX_MAX]; }; struct io_uring_zcrx_area_reg */ __u64 buffers_ptr; /** @buffer_count: Number of BO handles for the tiling parameters. */ enum { IFLA_MCTP_UNSPEC, IFLA_MCTP_NET, IFLA_MCTP_PHYS_BINDING, __IFLA_MCTP_MAX,
<justin.iurman@uliege.be> */ #ifndef QXL_DRM_H #define QXL_DRM_H #include "drm.h" #if defined(__cplusplus) extern "C" { #endif #define __NR_pidfd_send_signal 424 __SYSCALL(__NR_pidfd_send_signal, sys_pidfd_send_signal) #define __NR_io_uring_setup 425 __SYSCALL(__NR_io_uring_setup, sys_io_uring_setup) #define __NR_io_uring_enter (__X32_SYSCALL_BIT + 115) #define __NR_setgroups 116 #define __NR_setresuid 147 __SYSCALL(__NR_setresuid, sys_setresuid) #define __NR_getresuid 165 #define __NR_umount2 (__X32_SYSCALL_BIT + 452) #define __NR_map_shadow_stack 453 #define __NR_futex_wake 454 #define __NR_futex_wait 455 __SYSCALL(__NR_futex_wait,