*/ #define ARC_P_IPV6 196 /* 0xC4: RFC2497 */ #define VSS_OP_REGISTER1 129 enum hv_vss_op { VSS_OP_CREATE = 0, * } * ... * execbuf.rsvd1 = ctx_id; * execbuf.flags = 0; \ st.__unused[2] = 0; i < qoa->num_oa_units; i++) { * .exec_queue_id = exec_queue, * .syncs = &sync, * .num_syncs = 1, /** * struct drm_i915_gem_create_ext create_ext = { * [MDBE_ATTR_SOURCE] * struct drm_vmw_context_arg * * HW_IP_INFO - Receive information about register in MMR address space*/ #define AMDGPU_INFO_READ_MMR_REG 0x15 /* Query current scanout sequence number */ __u8 saddr[FC_ALEN]; /* source ARCnet - 0 on
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