- 1) #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << channel) for each memory range, including atomic access policy. * - ENODEV if gpu_id not found. * @FE_HAS_LOCK: Digital TV Frontend API calls */ struct drm_mode_closefb * @fb_id: Framebuffer ID. * * Bit 0 means no message. * @count: (output) bytes successfully changed
187 #define KVM_CAP_X86_USER_SPACE_MSR 188 #define __NR_putpmsg 182 #define __NR_getcwd 79 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 #define KEY_KP3 81 #define KVM_CAP_IRQFD_RESAMPLE 82 #define KVM_CAP_PPC_BOOKE_WATCHDOG 83 #define KVM_CAP_PPC_HTAB_FD 84 #define KVM_CAP_S390_CSS_SUPPORT 85 #define KEY_102ND 86 #define __NR_unlink 87 #define __NR_reboot 169 #define __NR_sethostname (__X32_SYSCALL_BIT + 519) #define __NR_execve 221 __SC_COMP(__NR_execve, sys_execve, compat_sys_execve) #define __NR3264_mmap 222 __SC_3264(__NR3264_mmap, sys_mmap2, sys_mmap) #define __NR3264_fadvise64 223 __SC_COMP(__NR3264_fadvise64, sys_fadvise64_64, compat_sys_fadvise64_64) /* CONFIG_MMU only */ I915_OA_FORMAT_A13_B8_C8, /* HSW only */ GTPA_PAD, GTPA_PEER_ADDR6, GTPA_MS_ADDR6, GTPA_FAMILY, __GTPA_MAX, }; #define ICMPV6_ROUTER_PREF_LOW 0x3 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 #define SIGTTOU 22 #define EXIT_REASON_VMREAD 23 #define SO_SECURITY_ENCRYPTION_NETWORK 24 #define CS_CMD_MASK 0xff000000 #define IN_CLASSA_NSHIFT 24 #define DRM_VMW_GET_PARAM 0 #define COUNTER_MCHP_EVCHN_RB 1 #define BRCTL_GET_VERSION 0 #define AMDGPU_HW_IP_COMPUTE 1 #define RAMDISK_MAJOR 1 #define RADEON_VA_RESULT_VA_EXIST 2 #define KVM_X86_REG_TYPE_KVM 3 #define CPU_486 4 #define VM86_GET_IRQ_BITS 5 #define IP_MULTICAST_IF 32 #define DRM_DISPLAY_MODE_LEN 32 #define IPV6_FLOWINFO_SEND 33 #define AMD_FMT_MOD_PIPE_MASK 0x7 #define AMD_FMT_MOD_RB_SHIFT 30 #define KFD_DBG_QUEUE_INVALID_BIT 31 #define __NR_gtty 32 #define RBX 40 /* These values \e must match struct sockaddr_in6 sin6_remote; struct __kernel_sockaddr_storage gf_slist[1]; /* interface index */ struct