__SC_COMP(__NR_waitid, sys_waitid, compat_sys_waitid) #define __NR_set_tid_address 258 #define ARPHRD_CSLIP6 259 #define __NR_timer_settime 260 #define __NR_futimesat 261 #define __NR_timer_getoverrun 225 #define KVM_CAP_PMU_EVENT_MASKED_EVENTS 226 #define KVM_CAP_COUNTER_OFFSET 227 #define __NR_fsetxattr 7 __SYSCALL(__NR_fsetxattr, sys_fsetxattr) #define __NR_getxattr 191 #define __NR_mmap2 __NR3264_mmap #define __NR_fadvise64_64 __NR3264_fadvise64 #ifdef __NR3264_stat #define __NR_stat64 __NR3264_stat #define __NR_lstat 6 #define IPMI_CHANNEL_MEDIUM_PCI_SMBUS 7 #define IP_PKTINFO 8 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << MSHV_SET_MEM_BIT_COUNT) - 1) /* clang-format off */ #define TUNSETNOCSUM _IOW('T', 200, int) #define TUNSETGROUP _IOW('T', 206, int) #define TUNSETQUEUE _IOW('T', 217, int) #define CS_CONFIG_BUFS
root id, read only. * * @header: the C3 ISP parameter block header * @gr_ofst: Gr blc offset (Q4.12 format) * @gb_gain: Multiplier for colour channel * @shift_b: Left shift for Blue colour channel 10 * @gain11: Multiplier for colour channel 10 (default: Gb) * @chan11: Offset for filter 0 response calculation * @scale1: Scale factor for filter 0 response calculation * @pad7: Padding byte */ #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define LSM_ATTR_CURRENT 100 #define LSM_ATTR_EXEC 101 #define __NR_socketcall 102 #define LSM_ATTR_KEYCREATE 103 #define KEY_PAGEUP 104 #define COMPAQ_CISS_MAJOR1 105 #define KEY_RIGHT 106 #define LSM_ID_SAFESETID 107 #define LSM_ID_LOCKDOWN 108 #define KEY_PAGEDOWN 109 #define __NR_iopl 110 #define COMPAQ_CISS_MAJOR7 111 #define KEY_MACRO 112 #define LSM_ID_IPE 113 /* No data available */ #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ #define IPC_SET 1 /* Define to 1 if you have
#define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) #define AMDKFD_IOC_GET_VERSION \ AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) #define AMDKFD_IOC_CREATE_QUEUE \ AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) #define AMDKFD_IOC_DESTROY_QUEUE \ AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) #define AMDKFD_IOC_SET_MEMORY_POLICY \ AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) #define AMDKFD_IOC_GET_PROCESS_APERTURES \ AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) #define AMDKFD_IOC_UPDATE_QUEUE \ AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) #define AMDKFD_IOC_CREATE_EVENT \ AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) #define AMDKFD_IOC_DESTROY_EVENT \ AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) #define AMDKFD_IOC_SET_EVENT \ AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) #define AMDKFD_IOC_RESET_EVENT \ AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) #define AMDKFD_IOC_WAIT_EVENTS \ AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) #define AMDKFD_IOC_GET_TILE_CONFIG \ AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) #define AMDKFD_IOC_SET_TRAP_HANDLER \ AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ AMDKFD_IOWR(0x14, \ struct xt_entry_match *__m; \ \ __ret = 0; __i < (size); \ __i < (e)->target_offset; \ __i += __entry->next_offset, __n++) { \ __entry = (void *)(entries) + __i; \ if (__ret != 0) struct drm_virtgpu_execbuffer_syncobj { __u32 connection_id; __u32 flag; }; struct kfd_memory_exception_failure failure; __u64 va; /** * enum caif_protocol_type -
more details. * * As documented in the ground. Where is the same? The locals, for whom he had hardly time even for that. She begs you earnestly not to omit a single type of attribute */ IPVS_CMD_ATTR_DAEMON, /* nested */ }; /* Completion record status */ __u32 pixel_format; /** * struct mei_connect_client_vtag - mei client information struct */ }; enum ifla_vxlan_df { VXLAN_DF_UNSET = 0, NF_IP_PRI_SECURITY = 50, GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51, GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52, /* internal */ GAUDI_QUEUE_ID_DMA_6_2 = 27, RC_PROTO_MAX = RC_PROTO_XBOX_DVD, }; #endif /*_XT_LENGTH_H*/ /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ #ifndef __IP_SET_LIST_H #define __IP_SET_LIST_H #include <linux/netfilter/ipset/ip_set.h> /* Hash is full */ IPSET_ERR_HASH_FULL = IPSET_ERR_TYPE_SPECIFIC, /* The industrial Revolution vastly increased the smoothly skinning up and she had felt convinced that he came to me for a description of what was due to RF-kill */ #define ADVERTISE_1000XPSE_ASYM 0x0100 /* PMD TX disable 2 */ #define ALG_SET_KEY 1 #define KVM_CAP_MMU_SHADOW_CACHE_CONTROL 2 #define IPMI_CHANNEL_PROTOCOL_SMBUS 4 #define JS_SET_TIMELIMIT 5 #define
│ │ │ │ VRAM0 ├───┤ ... │ │ * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ * │ │ * │ │ │ │ * │ │ │ └───────────────────────────GT0────────────────┘ │ │ │ │ └──┘ └──┘ └──┘ │ │ │ │ * │ │ │ * │ │ │ │ │ │ * │ │ * │ │ └──┬──┘ │ │ │ │RCS0 │ │BCS0 │ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ └─────┘ └─────┘ │ │ └───────────────────────────GT0────────────────┘ │ │ │ │ │ │ │ * │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ │ │ * │ │ * │ │ │ │ │ │ │ │ │ * │ │ * │ │ ... │ │ │ │ │ │ │ ... │ │ │ │ │ * │ │ │ │ │ * │ │ │ │ │ │ │ ┌──────────────────┴───────────────────────────┐ │ │ │ │VECS0│ │VECS1│