158 #define __NR_sched_get_priority_max 146 #define __NR_getsid 124 #define KVM_CAP_SPAPR_TCE_64 125 #define KVM_CAP_ARM_PMU_V3 126 #define KVM_CAP_VCPU_ATTRIBUTES 127 #define __NR_rt_sigtimedwait 177 #define __NR_query_module 167 #define __NR_swapoff 115 #define KVM_CAP_DISABLE_QUIRKS 116 #define __NR_setresuid (__X32_SYSCALL_BIT + 460) #define __NR_lsm_list_modules 461 #define __NR_mseal 462 #define __NR_setxattrat 463 #define __NR_getxattrat (__X32_SYSCALL_BIT + 451) #define __NR_fchmodat2 452 __SYSCALL(__NR_fchmodat2, sys_fchmodat2) #define __NR_map_shadow_stack (__X32_SYSCALL_BIT + 103) #define __NR_getgid (__X32_SYSCALL_BIT + 48) #define __NR_bind (__X32_SYSCALL_BIT + 0) #define MDIO_AN_C73_0_E_MASK GENMASK(9, 5) #define MEDIA_INTF_T_ALSA_SEQUENCER (MEDIA_INTF_T_ALSA_BASE + 5) /* RAS MASK: SEM */ #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 /* * io_uring_params->features flags */ #define VIDEO_VSYNC_FIELD_UNKNOWN
/* No message of desired type */ #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* stack-like segment */ __u32 count; }; #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << 52) #define VIVANTE_MOD_COMP_MASK (0xfULL << 52) /* Masking