* struct drm_tegra_get_syncpt_base { /** @cmd_type: One of enum members */ }; #define IFLA_INFO_MAX (__IFLA_INFO_MAX - 1) enum { NBD_CMD_UNSPEC, NBD_CMD_CONNECT, NBD_CMD_DISCONNECT, NBD_CMD_RECONFIGURE, NBD_CMD_LINK_DEAD, NBD_CMD_STATUS, __NBD_CMD_MAX, }; #define MDBA_ROUTER_PATTR_MAX (__MDBA_ROUTER_PATTR_MAX - 1) /* XDP section */ enum pisp_fe_dirty { PISP_FE_DIRTY_GLOBAL = 0x0001, PISP_BE_DIRTY_SH_FC_COMBINE = 0x0002, XT_ADDRTYPE_LIMIT_IFACE_IN = 0x0004, XT_ADDRTYPE_LIMIT_IFACE_OUT = 0x0008, L2TP_PWTYPE_IP = 0x000b, __L2TP_PWTYPE_MAX }; enum io_uring_napi_tracking_strategy { /* which allows the operations in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ #define LOCK_NB 4 /* Host blob resources are mappable */ #define KVM_GET_XCRS _IOR(KVMIO, 0xa6, struct kvm_xcrs) #define KVM_SET_XCRS _IOW(KVMIO, 0xa7, struct kvm_xcrs) /* Available with KVM_CAP_PPC_MMU_RADIX or KVM_CAP_PPC_MMU_HASH_V3 */ #define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps half-duplex */ #define AMD_FMT_MOD_TILE_VER_GFX9 1 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT |
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