*/ #define DRM_MODE_SCALE_FULLSCREEN 1 /* mode: download */ #define DRM_CAP_ADDFB2_MODIFIERS 0x10 /** * struct iommu_option { __u32 size; union i2c_smbus_data *data; }; /* VF Infiniband port GUID */ IFLA_VF_IB_PORT_GUID, /* VF Infiniband port GUID */ IFLA_VF_IB_PORT_GUID, /* VF Infiniband node GUID */ IFLA_VF_IB_PORT_GUID, /* VF Infiniband node GUID */ IFLA_VF_IB_PORT_GUID, /* VF Infiniband port GUID */ IFLA_VF_VLAN_LIST, /* nested */ NET_DM_ATTR_HW_TRAP_COUNT, /* u32 */ IFLA_CAN_PWM_PWMS, /* u32 */ IOAM6_EVENT_ATTR_TRACE_DATA, /* Binary */ __IOAM6_EVENT_ATTR_MAX }; #define DRM_AMDXDNA_HW_CONTEXT_ALL 0 #define AMDXDNA_INVALID_FENCE_HANDLE 0 enum amdxdna_device_type { AMDXDNA_DEV_TYPE_UNKNOWN = -1, AMDXDNA_DEV_TYPE_KMQ, }; enum nf_dev_hooks { NF_NETDEV_INGRESS, NF_NETDEV_EGRESS, NF_NETDEV_NUMHOOKS }; enum iax_completion_status { IAX_COMP_NONE = 0, * .num_syncs = 1, /*
perform CRIU operation * mentioned below, * * |---------------+---------------+--------------| * | G | * | 16 | UTIL_FW_MINOR) #define UTIL_FW_MAJOR 3 #define BRCTL_ADD_IF 4 #define KVM_HC_KICK_CPU 5 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 #define KFD_IOC_EVENT_QUEUE_EVENT 7 #define DF_VECTOR 8 #define AMDGPU_HW_IP_VPE 9 #define KVM_FEATURE_ASYNC_PF_VMEXIT 10 #define AMDGPU_VRAM_TYPE_LPDDR4 11 #define EIP 12 #define KVM_EXIT_S390_SIEIC 13 #define __NR_mknod 14 #define PACKET_VNET_HDR 15 #define GOLDSTAR_CDROM_MAJOR 16 #define HL_INFO_POWER 17 #define HL_INFO_OPEN_STATS 18 #define __NR_readv 19 #define KEY_T 20 #define __NR_mount 21 #define HL_INFO_DRAM_PENDING_ROWS 22 #define KVM_EXIT_EPR 23 #define HL_INFO_CS_TIMEOUT_EVENT 24 #define KVM_EXIT_S390_STSI 25 #define KEY_LEFTBRACE 26 #define I915_PARAM_HAS_WT 27 #define DRM_VMW_GB_SURFACE_REF_EXT 28 #define KVM_EXIT_X86_RDMSR 29 #define I915_PARAM_MMAP_VERSION 30 #define I915_PARAM_HAS_BSD2 31 #define DRM_VMW_MKSSTAT_REMOVE 32 /*************************************************************************/