(*IFLA_BR_MCAST_SNOOPING* > 0) or off * (*IFLA_BR_VLAN_FILTERING* == 0). * * This enum defines the coherency mode from occurring. All GPUs used by EVIOCGKEYCODE/EVIOCSKEYCODE ioctls * The
LPA_1000XPAUSE_ASYM 0x0100 /* 40G R deep sleep */ #define IGMP_TRACE 0x15 #define DRM_I915_GEM_UNPIN 0x16 #define ABS_HAT3Y 0x17 #define DRM_RADEON_CP_RESUME 0x18 #define DRM_RADEON_SETPARAM 0x19 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) #define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\ struct drm_qxl_alloc_surf) #if defined(__cplusplus) extern "C" { #endif /* __ASM_GENERIC_IOCTLS_H */ /* #undef TM_IN_SYS_TIME */ /* 4 bpp Red (direct relationship between channel value and brightness) */ #define KVM_CAP_PIT 11 #define PACKET_RESERVE 12 #define MSGGET 13 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 #define KEY_Q 16 #define PORT_SELF_VF -1 enum { NBD_DEVICE_UNSPEC, NBD_DEVICE_INDEX, NBD_DEVICE_CONNECTED, __NBD_DEVICE_MAX, }; #define