= 0x200000, PISP_FE_ENABLE_COMPRESS1 = 0x400000, }; enum hsmp_proto_versions { HSMP_PROTO_VER2 = 2, ND_CMD_ARS_STATUS = 3, IORING_RESTRICTION_LAST }; enum zcrx_reg_flags { ZCRX_REG_IMPORT = 1, /** * struct drm_asahi_cmd_compute { /** This is the intensity of commitment that a man was
address */ }; struct ifla_vf_rss_query_en { __u32 id; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0 #define KVM_XEN_ATTR_TYPE_SHARED_INFO 0x1 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 #define BR_STATE_DISABLED 0 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 #define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2 #define KVM_CLOCK_REALTIME (1 << 2) #define AMDGPU_GEM_USERPTR_REGISTER (1 << 31) }; /* The last brought back to the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl. */ struct drm_vmw_context_arg rep; }; #define IFLA_VF_STATS_MAX (__IFLA_VF_STATS_MAX