| LS1 | * | 2048 | 0,0 | 16,23 | LS2 | * | | | | | 00-07 | LS0 | * +-----------+------------+-------+--------------+ * | 63..48 | 47..32 | 31..16 | 15..0
to the * registration information; so define a bunch of things for manipulating the control register */ #define KEY_PASTE 135 /* AC Save */ #define HSA_IOLINK_TYPE_UNDEFINED 0 #define IPV6_FL_A_PUT 1 #define ALG_SET_IV 2 #define NFC_LLCP_REMOTE_LTO 3 #define KVM_MP_STATE_SIPI_RECEIVED 4 #define HSA_DBG_DISPATCH_INFO_ALWAYS_VALID 0x00000400 #define LIRC_CAN_REC_RAW LIRC_MODE2REC(LIRC_MODE_RAW) #define LIRC_CAN_REC_PULSE LIRC_MODE2REC(LIRC_MODE_PULSE) #define LIRC_CAN_REC_MODE2 LIRC_MODE2REC(LIRC_MODE_MODE2) #define LIRC_CAN_REC_SCANCODE LIRC_MODE2REC(LIRC_MODE_SCANCODE) #define LIRC_CAN_REC_LIRCCODE LIRC_MODE2REC(LIRC_MODE_LIRCCODE) #define LIRC_CAN_REC_MASK LIRC_MODE2REC(LIRC_CAN_SEND_MASK) #define LIRC_CAN_SET_REC_CARRIER (LIRC_CAN_SET_SEND_CARRIER << 16) /* use netfilter conntrack */ /* #undef HAVE_SYS_LOCK_H */ /* SCSI-tape specific definitions */ #define IOPRIO_HINT_SHIFT IOPRIO_LEVEL_NR_BITS #define IOPRIO_HINT_NR_BITS 10 #define EXIT_REASON_HLT 12 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4 #define DRM_I915_QUERY_HWCONFIG_BLOB 5 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 #define DRM_VMW_MKSSTAT_RESET 30 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 #define DTV_ISDBT_LAYERC_MODULATION 32 #define EXIT_REASON_INVALID_STATE 33 #define SO_KEEPALIVE 9 #define AMDGPU_HW_IP_NUM 10 #define