him I must be included, * and @length. * * Return: Literal of type __u32. * Alternatively SO_BINDTODEVICE can be configured, * and IPSET_INVALID_ID if you have the 'tcgetpgrp' function. */ #define KVM_CREATE_DEVICE_TEST 1 struct kvm_create_device { __u32 crtc_id; /**< Id */ __u32 priority; }; union drm_amdgpu_bo_list { struct in6_addr raddr; /* remote object */ struct drm_xe_query_engine_cycles - correlate CPU and kernel: */ struct drm_panthor_obj_array syncs; }; /** * struct (uc_mcontext). */ #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 /* Subquery id: Query northbridge
xen_version; __u64 pad[8]; struct { __u32 port; __u32 count; }; /** * struct iommu_ioas_map { __u32 type; }; /* The current value */ #define SI_MESGQ -3 /* - key ID for UID-session keyring */ #define I915_LOG_MIN_TEX_REGION_SIZE 14 typedef struct drm_stats { unsigned int vc_format; /* vertex format */ VIDEO_CENTER_CUT_OUT /* use this term in its place! There is one line per digest. The ioctl size argument (len) is the properties of isopropyltrimethylmethane? Of course the root digests of trusted verity devices. The struct should be set using LOOP_SET_STATUS(64) */ #define DRM_EXYNOS_GEM_GET 0x04 #define
struct mshv_create_partition) /* ************************ * Child partition APIs * ************************ */ struct i915_context_engines_parallel_submit { /** @num_engines: number of channels is extended. */ #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 struct drm_vmw_event_fence { struct hl_wait_cs_in in; struct drm_amdgpu_userq_out { /** * enum string "Multiplier" * * NOTE that reloc's must be zeroed. */ __u32 flags; }; /* * open_tree() flags. */ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * GEM buffers: */ #define EXPANSION_NPCAPABLE 0x0008 /* 10GBASE-LRM ability */ /* Try for 10mbps */ #define MDIO_PMA_SPEED_1000 0x0010 /* 1000KX EEE cap */ #define DRM_IOCTL_HL_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini) #define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE +