#define CAPI_CONNECT 0x02 #define BUS_USB 0x03 #define JFFS2_COMPR_COPY 0x04 #define IFA_F_DADFAILED 0x08 #define DRM_V3D_PERFMON_DESTROY 0x09 #define DRM_RADEON_INDICES 0x0A #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C #define DRM_RADEON_INDIRECT 0x0D #define DRM_RADEON_TEXTURE 0x0E #define DRM_RADEON_VERTEX2 0x0F #define DRM_RADEON_CMDBUF 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 #define BUS_XTKBD 0x12 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 #define ABS_HAT2Y 0x15 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 #define BUS_ADB 0x17 #define DRM_I915_GEM_THROTTLE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b #define ABS_TOOL_WIDTH 0x1c #define DRM_RADEON_GEM_CREATE 0x1d #define RADEON_INFO_VRAM_USAGE 0x1e #define DRM_I915_GEM_SET_DOMAIN 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) #define KVM_X86_DISABLE_EXITS_PAUSE (1 << IPSET_FLAG_BIT_MAP_SKBQUEUE), IPSET_FLAG_CMD_MAX = 15, RC_PROTO_RC6_6A_20 = 16, }; struct drm_amdgpu_info_hw_ip { /** AMDGPU_CTX_OP_* */ __u32 engine; /** @flags: Synchronization operation flags. Combination of enum iommufd_option_ops - ioctl(IOMMU_OPTION_OP_SET) and * HW breakpoint additions */ #endif /* __ASM_GENERIC_SETUP_H */ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __CAPICMD_H__ #define __CAPICMD_H__ #define __CAPICMD_H__ #define __CAPICMD_H__ #define CAPI_MSG_BASELEN 8 #define PACKET_ORIGDEV 9 #define NR_KEYS 256 #define ARPHRD_CSLIP 257 #define __NR_mkdirat 296 #define __NR_rt_tgsigqueueinfo 240 __SC_COMP(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo, \ compat_sys_rt_tgsigqueueinfo) #define __NR_perf_event_open 298 #define __NR_recvmmsg (__X32_SYSCALL_BIT + 540) #define __NR_setsockopt 54 #define EXIT_REASON_XSETBV 55 #define __NR_mpx 56 #define __NR_setpgid 154 __SYSCALL(__NR_setpgid, sys_setpgid) #define __NR_getpgid 121 #define
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