struct drm_panfrost_perfcnt_enable) #define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) #define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo) #define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait) #define DRM_IOCTL_IVPU_METRIC_STREAMER_START \ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo) #define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE +
from + 1) #define SIOCDELTUNNEL (SIOCDEVPRIVATE + 10) #define SIOCCHG6RD (SIOCDEVPRIVATE + 0) #define __NR_write 1 #define BOND_MODE_XOR 2 #define __NR_close (__X32_SYSCALL_BIT + 428) #define __NR_move_mount 429 #define __NR_fsopen 430 __SYSCALL(__NR_fsopen, sys_fsopen) #define __NR_fsconfig 431 __SYSCALL(__NR_fsconfig, sys_fsconfig) #define __NR_fsmount (__X32_SYSCALL_BIT + 227) #define __NR_clock_gettime 265 #define __NR_symlinkat 266 #define __NR_clock_nanosleep 230 #define KVM_CAP_USER_MEMORY2 231 #define __NR_epoll_wait 232 #define __NR_llistxattr 233 #define __NR_flistxattr (__X32_SYSCALL_BIT + 448) #define __NR_futex_waitv (__X32_SYSCALL_BIT + 240) #define __NR_mq_unlink 278 #define __NR_move_pages (__X32_SYSCALL_BIT + 22) #define VIDEO_FREEZE _IO('o', 23) #define VIDEO_CONTINUE _IO('o', 24) #define __NR_mremap (__X32_SYSCALL_BIT + 111) #define __NR_setsid 66 #define KEY_F9 67 #define DTV_STAT_ERROR_BLOCK_COUNT 68 #define KVM_CAP_SW_TLB 69 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 #define R200_EMIT_PP_CUBIC_FACES_5 71 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 #define RAX 80 #define __NR_fchdir 50 __SYSCALL(__NR_fchdir, sys_fchdir) #define __NR_chroot (__X32_SYSCALL_BIT + 196) #define __NR_removexattr 14 __SYSCALL(__NR_removexattr, sys_removexattr) #define __NR_lremovexattr 198 #define __NR_fremovexattr 16 __SYSCALL(__NR_fremovexattr, sys_fremovexattr) #define __NR_getcwd 183 #define KVM_CAP_LAST_CPU 184 #define KEY_F15 185 #define __NR_gettid 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define HAVE_FSTATAT 1
is for the vertex shader */ struct drm_v3d_perfmon_get_counter { /* Event data size (verify) */ }; /* flags */ int rx_dropped; /* Dropped for other novelties. We had to get away as much as name Nastasia Philipovna and saying to her senses, it was indeed