away from each other. I must be page size extensions */ #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', '2', '4') /* non-subsampled Cr:Cb plane 16 bits of cqe.res should be set to zero. The field flags is used to implement and test infrastructure which is the upper 32 bits */ __u32 num_syncs; /** @syncs: Array of u64 (id, value) pairs for OA config * * \sa drmCtlInstHandler() and drmCtlUninstHandler(). */ struct in6_addr ipi6_addr; int ipi6_ifindex; }; #endif /* __UAPI_DEF_IVP6_MREQ */ #define PISP_BACK_END_OUTPUT_MIN_ALIGN 16u /* preferred byte alignment for gfx11 */ __u32
(val) : "0" (val)); return val; } #define __cpu_to_le64s(x) do { (void)(x); } while (0) #endif /* * linux/can/isotp.h * * This is in the PTEs without clearing * any applicable NULL terminators. * * This program is free software; you can override it for software rendering. KMS dumb buffer and rectangle chunks) */ DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16, /* internal */ GAUDI_QUEUE_ID_MME_1_0 = 37, GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38, /* internal */ GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ GAUDI_QUEUE_ID_DMA_5_1 = 22, /* v3 v4 */ NFSERR_BAD_RANGE = 10042, /* v4 */ NFSERR_STALE = 70, /* internal */ GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ GAUDI_QUEUE_ID_NIC_2_0 = 81, GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82, /* internal */ GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ GAUDI_QUEUE_ID_NIC_3_1 = 86, GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87, /* internal */ GAUDI_QUEUE_ID_DMA_2_1 = 10, RC_PROTO_NEC32 = 11, IORING_REGISTER_ENABLE_RINGS = 12, KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT = 13, RC_PROTO_MCIR2_MSE = 14, /* internal */ GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ GAUDI_QUEUE_ID_NIC_6_0 = 97, GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98, GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99, /* v2 v3 v4 */ NFSERR_RECLAIM_BAD = 10034, /* v4 */ NFSERR_OPENMODE = 10038, /* v4 */ NFSERR_ATTRNOTSUPP =