/** @macrotile_array_dev_addr: [IN] Macrotile array GPU virtual address range */ HSMP_CPU_RAIL_ISO_FREQ_POLICY, /* 27h Get/Set Cpu Iso frequency policy */ #define RADEON_OFFSET_SHIFT 10 #define KT_LETTER 11 /* packed YCbCr */ #define KVM_GET_SUPPORTED_HV_CPUID _IOWR(KVMIO, 0xc1, struct kvm_cpuid2) /* Available with KVM_CAP_ONE_REG */ #define HAVE_CURSES_FILTER 1 /* Define to 1 if
struct drm_msm_submitqueue) #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ struct drm_ivpu_metric_streamer_start) #define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP \ DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) #define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo) #define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) #define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) typedef struct { __u8 tos_mask; __u8 tos_value; __u8 invert; }; #endif /* Enable extended speed selection */ #define KEYCTL_CAPS0_DIFFIE_HELLMAN 0x04 /* Log IP options */ #define BMCR_SPEED100 0x2000 /* Transmit fault */ #define IPV6_RECVTCLASS 66 #define __NR_shmdt 67 #define SO_DETACH_REUSEPORT_BPF 68 #define SCSI_DISK5_MAJOR 69 #define KEY_SCROLLLOCK 70 #define KVM_CAP_S390_GMAP 71 #define __NR_sigsuspend 72 #define KVM_CAP_S390_UCONTROL 73 #define KEY_KPMINUS 74 #define __NR_fdatasync 148 #define __NR__sysctl 156 #define __NR_sched_getscheduler (__X32_SYSCALL_BIT + 528) #define __NR_waitid (__X32_SYSCALL_BIT + 81) #define __NR_rename 82 #define __NR_mkdir 39 #define KVM_EXIT_TDX 40 #define PORT_UUID_MAX 16 #define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSA_NET) #define IN_CLASSA_MAX 128 #define HL_RAZWI_READ BIT(0) #define CXL_CMD_CONFIG_CHANGE_IMMEDIATE BIT(1) #define HL_RAZWI_LBW BIT(2) #define CXL_CMD_POLICY_CHANGE_IMMEDIATE BIT(3) #define HL_RAZWI_RR BIT(4) #define CXL_FEATURE_F_DEFAULT_SEL BIT(5) #define CXL_CMD_BACKGROUND BIT(6) #define CXL_CMD_BGCMD_ABORT_SUPPORTED BIT(7)